Equalizer

ABSTRACT

An equalizer includes a data sampler that samples input data and outputs a time-series data string according to the input data, an arithmetic circuit that multiplies a data string output before reference data in the data string output from the data sampler by a tap coefficient and forms the input data by an arithmetic operation of a multiplication result and an input signal, a tap coefficient calculation circuit that updates the tap coefficient based on a data string output before the reference data, and a determination circuit that receives the reference data and data output after the reference data in the data string and controls presence or absence of update of the tap coefficient performed by the tap coefficient calculation circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an equalizer, in particular, to atechnique for adjusting a waveform equalization coefficient of adecision feedback equalizer.

2. Description of the Related Art

There are many types of equalizers. Among them, there is a decisionfeedback equalizer (DFE). The decision feedback equalizer is known asone of waveform equalization techniques for compensating transmissionloss. In the decision feedback equalizer, adjustment of the waveformequalization coefficient is performed to compensate the transmissionloss. As techniques related to the adjustment of the waveformequalization coefficient, for example, techniques described in IEEETransactions on Communications, Vol. COM-29, No. 11, November 1981 andJP-2011-151765-A are known.

IEEE Transactions on Communications, Vol. COM-29, No. 11, November 1981describes a technique that adaptively adjusts a filter response byselecting a corresponding filter response from a table in a memory whenreceiving a transmission signal and performing feedback so as tosubtract an output of the selected filter response from a receptionsignal. JP-2011-151765-A describes a technique that performs filteringso as to equalize the number of occurrences of each bit pattern which abit string can form.

SUMMARY OF THE INVENTION

Data is serially transmitted between information devices, such asbetween a server and a router. Along with speeding up these days, thespeed of transmitting data (the transmission speed) is also increasing.For example, the transmission speed per transmission line exceeds 10Gbps. In such a high transmission speed, the loss in the transmissionline increases and a bit error rate increases in transmitted data.

To reduce the bit error rate, a waveform loss generated in atransmission line is compensated by an equalizer (a waveform equalizer).In this case, the waveform equalizer is provided in a receiver circuitthat receives data propagated in the transmission line and/or a drivercircuit that transmits data to the transmission line. As describedabove, there are many types of waveform equalizers (equalizers). Forexample, there are a decision feedback equalizer, a feed forwardequalizer (FFE), and a continuous time linear equalizer (CTLE).

When the waveform equalizers are provided in a receiver circuit and/or adriver circuit, for example, some types of equalizers are selected fromthe waveform equalizers described above and the selected equalizers arecombined and provided so that effects of these equalizers are exerted.

Among the many types of equalizers described above, the decisionfeedback equalizer equalizes an effect of a symbol transferred before asymbol to be transmitted, that is, an effect of a post-cursor, ofintersymbol interference that is a main component of the waveform loss.On the other hand, the decision feedback equalizer does not equalize aneffect of a symbol transferred after a symbol to be transmitted, thatis, an effect of a pre-cursor.

Specifically, in the decision feedback equalizer, data of a symboltransferred before a symbol to be transmitted is multiplied by a tapcoefficient and data obtained by this multiplication is subtracted fromdata of the symbol to be transmitted. Thereby, equalization of theeffect of the post-cursor is performed. However, equalization of theeffect of the pre-cursor is not performed.

On the other hand, in a least mean square (LMS) algorithm used for thedecision feedback equalizer, when the tap coefficient is determined, adegree of contribution of each tap tends to be reduced. Therefore, whenthe effect of the pre-cursor is large, there is a problem that theconvergence characteristics of the tap coefficient become unstable.

In IEEE Transactions on Communications, Vol. COM-29, No. 11, November1981 and JP-2011-151765-A, the effect of the pre-cursor is notrecognized.

An object of the present invention is to provide an equalizer that canimprove the convergence accuracy of tap coefficient and shorten theconvergence time.

Other purposes and new features of the present invention will becomeclear from the description of the present specification and theaccompanying drawings.

The following explains briefly the outline of a typical invention amongthe inventions disclosed in the present application.

According to an embodiment, an equalizer includes a data sampler, anarithmetic circuit, a tap coefficient calculation circuit, and adetermination circuit. Here, the data sampler samples input data andoutputs a time-series data string according to the input data. Thearithmetic circuit multiplies a data string output before reference datain the data string output from the data sampler by a tap coefficient andforms the input data described above by an arithmetic operation of amultiplication result and an input signal. The tap coefficientcalculation circuit updates the tap coefficient based on a data stringoutput before the reference data. The determination circuit receives thereference data and data output after the reference data in the datastring and controls the presence or absence of update of the tapcoefficient performed by the tap coefficient calculation circuit.

According to another embodiment, an equalizer includes an input bufferthat receives an input signal, a decision feedback equalizer including adata sampler and an error sampler, and a tap coefficient calculationcircuit that receives a data output from the data sampler and an erroroutput from the error sampler and adaptively calculates a tapcoefficient in the decision feedback equalizer. Here, the equalizerincludes a filter circuit that receives data of a predetermined onesymbol to be reference data in the data output from the data sampler anddata one symbol after the predetermined one symbol, and the presence orabsence of update of the tap coefficient in the tap coefficientcalculation circuit is determined according to a result of the filtercircuit.

The presence or absence of update of the tap coefficient is determinedby a relationship between a code of the reference data (data of apredetermined one symbol) and a code of data output after the referencedata (data output one symbol after the reference data). That is to say,the tap coefficient used when equalizing the reference data is acoefficient where the code of the reference data and the code of dataoutput after the reference data are considered. As a result, it ispossible to improve the accuracy (convergence accuracy) of the tapcoefficient when the tap coefficient converges. Further, it is possibleto shorten a time (a convergence time) required for the convergence.

The following explains briefly the effects obtained by a typicalinvention among the inventions disclosed in the present application.

Even in a state in which the pre-cursor remains, it is possible toprovide an equalizer that can improve the convergence accuracy of tapcoefficient and shorten the convergence time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of a receivercircuit according to a first embodiment;

FIGS. 2A to 2C are waveform charts schematically illustrating anoperation of a decision feedback equalizer;

FIG. 3 is a waveform chart illustrating a waveform of input data outputfrom a tap adding circuit according to the first embodiment;

FIG. 4 is a block diagram illustrating configurations of a tapcoefficient calculation circuit and a filter circuit according to thefirst embodiment;

FIG. 5 is a block diagram illustrating a configuration of a filtercircuit according to a modified example of the first embodiment;

FIG. 6 is a block diagram illustrating a configuration of a filtercircuit according to a second embodiment;

FIG. 7 is a waveform chart illustrating a waveform of input data outputfrom a tap adding circuit according to the second embodiment;

FIG. 8 is a block diagram illustrating a configuration of a receivercircuit according to a third embodiment;

FIG. 9 is a block diagram illustrating a configuration of a tapcoefficient calculation circuit according to the third embodiment; and

FIG. 10 is a waveform chart illustrating a waveform of output dataoutput from a data sampler.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described indetail with reference to the drawings. In all the drawings fordescribing the embodiments, the same portions are denoted by the samereference symbols in principle and repetitive descriptions thereof willbe omitted in principle.

First Embodiment

FIG. 1 is a block diagram illustrating a configuration of a receivercircuit according to a first embodiment. In FIG. 1, reference numeral101 denotes a receiver circuit. The receiver circuit 101 is connected toa transmission line DL, and a driver circuit DV that outputstransmission data DT is connected to the transmission line DL.

The driver circuit DV generates a time-series data string and suppliesthe data string to the transmission line DL as the transmission data DT.In other words, the driver circuit DV supplies a serial data string (abit string) to the transmission line DL. The data string supplied to thetransmission line DL propagates in the transmission line DL and issupplied to the receiver circuit 101.

At this time, the transmission line DL has a loss, so that a waveform ofeach data (bit) of the transmission data DT supplied to the receivercircuit 101 is deformed and is further deformed by mutual interferencebetween data. As a result, the waveform of the transmission data DTsupplied to the receiver circuit 101 is deformed due to a waveform lossgenerated by the transmission line DL.

The receiver circuit 101 receives the supplied transmission data DT,equalizes the waveform loss generated by the transmission line DL, andoutputs output data DD0 corresponding to the transmission data DT outputfrom the driver circuit DV. Although the receiver circuit 101 includes aplurality of circuits, FIG. 1 illustrates only an input buffer 102 andan equalizer EQ and omits the other circuits.

The equalizer EQ includes a decision feedback equalizer (hereinafteralso referred to as a DFE circuit) 103, a demultiplexer 104, a tapcoefficient calculation circuit 105 that adaptively calculates a tapcoefficient, and a filter circuit 106. For convenience of description,the equalizer EQ includes the circuit block described above in thedescription. However, the decision feedback equalizer 103 may be assumedto be the equalizer EQ. In this case, the demultiplexer 104, the tapcoefficient calculation circuit 105, and the filter circuit 106 may beassumed to be circuits attached to the equalizer EQ.

The transmission data DT is input into the decision feedback equalizer103 through the input buffer 102. The input buffer 102 is, for example,an equalizer which is different from the decision feedback equalizer.For example, the input buffer 102 is a continuous time linear equalizeror the like. Of course, the input buffer 102 need not be included or maybe a buffer that shapes the waveform of the transmission data DT.

The decision feedback equalizer 103 includes a data sampler 121, anerror sampler 122, a bit shift circuit 123, a tap coefficientmultiplying circuit 124, and a tap adding circuit 125.

The tap coefficient multiplying circuit 124 is composed of a pluralityof tap coefficient multipliers 124-1 to 124-n, each of which has thesame configuration. The tap coefficient multipliers 124-1 to 124-nrespectively multiply corresponding output data B1 to Bn (data stringSB) from the bit shift circuit 123 by corresponding tap coefficientsTap1 to Tapn. FIG. 1 representatively illustrates the tap coefficientmultipliers 124-1, 124-2, and 124-n of the plurality of tap coefficientmultipliers included in the tap coefficient multiplying circuit 124. Thetap coefficient multiplier 124-1 will be described as an example. Thetap coefficient multiplier 124-1 performs multiplication of acorresponding tap coefficient Tap1 and corresponding output data B1 fromthe bit shift circuit 123. The same goes for the other tap coefficientmultipliers 124-2 to 124-n.

An output signal from the tap coefficient multiplying circuit 124, thatis, an output signal (a multiplication result) of each of the tapcoefficient multipliers 124-1 to 124-n, is supplied to the tap addingcircuit 125. The tap adding circuit 125 uses a signal output from theinput buffer 102 as an input signal, performs subtraction between theinput signal and the output signal (the multiplication result) from thetap coefficient multiplying circuit 124, and supplies a signal obtainedby the subtraction to the data sampler 121 and the error sampler 122 asan input data IW. In the present specification, both subtraction andaddition are referred to as addition unless otherwise stated.

Here, the tap coefficient multiplying circuit 124 and the tap addingcircuit 125 can be assumed to be an arithmetic circuit that multipliesthe output data B1 to Bn of the bit shift circuit 123 by the tapcoefficients Tap1 to Tapn, respectively, and adds (subtracts) an outputsignal (a multiplication result) obtained by the multiplication to(from) an input signal.

The data sampler 121 samples the input data IW output from the tapadding circuit 125, that is, the input data IW output from thearithmetic circuit, in a state in which there is no data offset. In FIG.1, the offset is indicated as zero to illustrate a state in which thereis no data offset. A data output obtained by the sampling of the datasampler 121, that is, a data string SD in FIG. 1, is supplied to the bitshift circuit 123 and the demultiplexer 104. On the other hand, theerror sampler 122 samples the input data IW in a state in which theinput data IW has a data offset Vof. In other words, the error sampler122 performs the sampling by comparing the input data IW with referenceto the data offset Vof. An error output obtained by the sampling, thatis, an error data string Error in FIG. 1, is supplied to thedemultiplexer 104 as a result of error sampling.

The bit shift circuit 123 includes a plurality of delay circuitsserially connected to each other. In FIG. 1, the plurality of delaycircuits are formed of flip-flop circuits (hereinafter also referred toas FF circuits) FF1 to FFn−1. Specifically, the FF circuits FF1 to FFn−1are serially connected to each other and each of the FF circuits FF1 toFFn−1 takes in data supplied to an input and outputs the data insynchronization with a clock signal not illustrated in FIG. 1. Thereby,each of the FF circuits FF1 to FFn−1 operates as a delay circuit havinga delay time according to the frequency of the clock signal. FIG. 1illustrates only the FF circuits FF1 and FFn−1 and omits the other FFcircuits FF2 to FFn−2.

The data string SD is supplied to the input of the FF circuit FF1included in the bit shift circuit 123, an output from the FF circuit FF1is supplied to the input of the FF circuit FF2 not illustrated in FIG.1, and an output from the FF circuit FF2 is supplied to the input of theFF circuit FF3 not illustrated in FIG. 1. The other FF circuits FF3 toFFn−1 are also serially connected to each other in the same manner. Aninput to the FF circuit FF1 is output as the output data B1 of the bitshift circuit 123, and an output from the FF circuit FF1, that is, aninput to the FF circuit FF2 (not illustrated in FIG. 1) is output as theoutput data B2. Similarly, each input to each of the FF circuits FF3 toFFn−1 is output as output data B3 to Bn−1. Further, an output from theFF circuit FFn−1 is output as the output data Bn of the bit shiftcircuit 123.

The bit shift circuit 123 receives time-series data string SD from thedata sampler 121 and outputs the data string SB composed of the outputdata B1 to Bn. In this case, the data string SB represents datatemporally sequentially output (in the past) from the data sampler 121in order from the output data B1 to the output data Bn. For example, inthe data string SB output from the bit shift circuit 123, the outputdata B2 represents data output from the data sampler 121 earlier thanthe output data B1. In the same manner, the output data of the datastring represents data temporally sequentially output from the datasampler 121 in order from the output data B3 to the output data Bn.

As described above, the tap coefficient multiplying circuit 124multiplies the output data B1 to Bn of the bit shift circuit 123 and thetap coefficients Tap1 to Tapn that are corresponding outputs from thetap coefficient calculation circuit 105. The tap adding circuit 125 addsa total sum of the outputs of the tap coefficient multiplying circuit124 to an input signal of the decision feedback equalizer 103. Theconfiguration of the decision feedback equalizer 103 illustrated in FIG.1 is an example and the configuration is not limited to this example.For example, the decision feedback equalizer 103 may be a speculativedecision feedback equalizer. Further, the frequency of the clock signalthat drives the decision feedback equalizer 103, for example, the clocksignal to which the FF circuits FF1 to FFn−1 synchronize, may be a halfrate or a quarter rate of a reference clock signal.

The data sampler 121 samples the input data IW (without data offset) andoutputs the input data IW. Therefore, the data string SD output from thedata sampler 121 is a data string composed of serial data D−1 to Dncorresponding to a temporal change of the input data IW, and the datastring SD is output serially (in series) from the data sampler 121 tothe demultiplexer 104. Similarly, the error sampler 122 samples theinput data IW (with data offset Vof) and outputs the error data stringError. Therefore, the error data string Error output from the errorsampler 122 is a data string composed of serial error data E−1 to Encorresponding to a temporal change of the input data IW, and the errordata string Error is output serially (in series) from the error sampler122 to the demultiplexer 104.

Here, the data sampler 121 and the error sampler 122 perform thesampling in synchronization with each other. Therefore, the data D−1 toDn that form the data string SD and the error data E−1 to En correspondto each other, respectively. In other words, the data D−1 and the errordata E−1 are data that are obtained by sampling the input data IW at thesame time, the data D0 and the error data E0 are data that are obtainedby sampling the input data IW at the same time, and the data D1 and theerror data E1 are data that are obtained by sampling the input data IWat the same time. The same goes for the other data D2 to Dn and theother error data E2 to En.

The data string SD from the data sampler 121 and the error data stringError from the error sampler 122 are outputs from the decision feedbackequalizer 103.

The demultiplexer 104 includes a holding circuit DH and converts thedata string SD and the error data string Error output from the decisionfeedback equalizer 103 into parallel data (temporally parallel data),respectively. Specifically, the output data SD of the data sampler 121is converted into parallel data and becomes parallel data strings (bitstrings) formed by the data D−1, D0, and D1 to Dn. Similarly, the errordata string Error of the error sampler 122 is converted into paralleldata and becomes parallel data strings (bit strings) formed by the dataE−1, E0, and E1 to En.

The holding circuit DH included in the demultiplexer 104 includes dataholding circuits dp, d0 to dn, and e0. Here, the data holding circuit dpcorresponds to the data D−1, and the data holding circuits d0 to dncorrespond to the data D0 to Dn, respectively. The data holding circuite0 corresponds to the error data E0 of the error data string Error. Thedata D−1 to Dn converted into parallel data are held by correspondingdata holding circuits dp and d0 to dn, respectively.

In the error data string Error output from the error sampler 122, errordata used in the tap coefficient calculation circuit 105 is only theerror data E0 corresponding to the reference data D0 to be equalized.Therefore, only the error data E0 corresponding to the reference data D0is held by the data holding circuit e0, and the other data E−1 and E1 toEn are, for example, not held by the holding circuit DH and they arediscarded.

FIG. 10 is a waveform chart illustrating a waveform of the data stringSD (data D−1 to Dn) output from the data sampler 121. In FIG. 10, thehorizontal axis represents time and the vertical axis represents avoltage. In FIG. 10, when the time t0 is defined as a reference time,the times t1 to tn represent times before the reference time t0, thatis, past times, and the time t−1 represents a time after the referencetime t0. For example, the time t1 represents a time before the referencetime t0 and the time t2 represents a time before the time t1. The samegoes for the times t3 to tn. In FIG. 10, for description purposes, eachof the reference data D0 at the reference time t0, the data D1 to Dn atthe times t1 to tn before the reference time t0, and the data D−1 at thetime t−1 after the reference time t0 represents a state of high levelcorresponding to, for example, a code of logical value 1. However, thecode (logical value) of each of the reference data D0, the data D1 to Dnafter the reference data D0, and the data D−1 before the reference dataD0 varies according to the value of the input data IW.

The input data IW is according to transfer data supplied from the drivercircuit DV (FIG. 1) to the transmission line DL. Therefore, the code ofthe reference data D0 corresponds to the code of the transfer datasupplied to the transmission line DL by the driver circuit DV at apredetermined time (for example, at the reference time t0). The code ofthe data D1 corresponds to the code of a symbol output by the drivercircuit DV one symbol before the reference data D0. Similarly, the codeof the data D2 corresponds to the code of a symbol output by the drivercircuit DV two symbols before the reference data D0. Similarly, the dataDn corresponds to a symbol n symbols before the reference data D0. Onthe other hand, the code of the data D−1 corresponds to the code of asymbol output to the transmission line DL by the driver circuit DV onesymbol after the reference data D0.

Although not illustrated in FIG. 10, in the same manner as in the datastring SD, in the error data string Error output from the error sampler122, the error data E0 is output from the error sampler 122 at thereference time t0. The error data E1 to En are output from the errorsampler 122 at the times t1 to tn, respectively, before the referencetime t0, and the error data E−1 is output from the error sampler 122 atthe time t−1 after the reference time t0.

A serial bit string (Dn to D−1) supplied from the time t0 to the timet−1 is converted into parallel data, the code (logical value) of thedata D−1 is held by the data holding circuit dp, and the data D0 to Dnare held by the data holding circuits d0 to dn. In the error data. E−1to En that are converted into parallel data, the code of the error dataE0 corresponding to the reference data D0 is held by the data holdingcircuit e0.

Here, output data B1 output from the bit shift circuit 123 correspondsto the data D1 held by the holding circuit DH, and output data B2 outputfrom the bit shift circuit 123 corresponds to the data D2 held by theholding circuit DH. In the same manner, output data B3 to Bn output fromthe bit shift circuit 123 respectively correspond to the data D3 to Dnheld by the holding circuit DH. In FIG. 10, for example, at the timet−1, the data string SD and the error data string Error are convertedinto parallel data, and the data D−1 to Dn and the error data E0 areheld by the holding circuit DH. On the other hand, the output data B1 toBn corresponding to the data D1 to Dn are output from the bit shiftcircuit 123.

The data string (the data D−1 to Dn) held by the holding circuit DH andthe error data E0 are output from the demultiplexer 104. The output fromthe demultiplexer 104 is supplied to the tap coefficient calculationcircuit 105 and the filter circuit 106. The reference data D0 is outputas an output DD0 of the receiver circuit 101.

In the first embodiment, the data D1 to Dn and the error data E0 in thebit string from the demultiplexer 104 are supplied to the tapcoefficient calculation circuit 105. The reference data D0 and the dataD−1 one symbol after the reference data D0 are supplied to the filtercircuit 106. Although the filter circuit 106 will be described laterwith reference to FIG. 4, the filter circuit 106 controls the presenceor absence of update of the tap coefficients Tap1 to Tapn in the tapcoefficient calculation circuit 105 based on the code of each of thereference data D0 and the data D−1 one symbol after the reference dataD0. The filter circuit 106 determines the presence or absence of updateof the tap coefficients Tap1 to Tapn, so that the filter circuit 106 canbe assumed to be a determination circuit.

When the update of the tap coefficients Tap1 to Tapn is set to beeffective (allowed) by the filter circuit 106, the tap coefficientcalculation circuit 105 updates the tap coefficients Tap1 to Tapn basedon the data D1 to Dn and the error data E0 from the demultiplexer 104.On the other hand, when the update of the tap coefficients Tap1 to Tapnis prohibited by the filter circuit 106, the tap coefficient calculationcircuit 105 does not update the tap coefficients Tap1 to Tapn. Theupdate of the tap coefficients Tap1 to Tapn includes a case in which thevalues of the tap coefficients are increased and a case in which thevalues of the tap coefficients are decreased.

In the first embodiment, the tap coefficient calculation circuit 105performs calculation (update) of the tap coefficient on the referencedata D0 by using data (D1 to Dn) of symbols before the reference dataD0, and the data string (B1 to Bn) before the reference data D0 ismultiplied by the tap coefficient. Then, the presence or absence of thecalculation (update) of the tap coefficient is controlled based on thereference data D0 and the data D−1 of a symbol after the reference dataD0. In an example of FIG. 4 described later, when the code of thereference data D0 and the code of the data D−1 one symbol after thereference data D0 are coincident with each other, the calculation(update) of the tap coefficient in the tap coefficient calculationcircuit 105 is allowed by the filter circuit 106. On the other hand,when the code of the reference data D0 and the code of the data D−1 onesymbol after the reference data D0 are not coincident with each other,the calculation (update) of the tap coefficient in the tap coefficientcalculation circuit 105 is prohibited by the filter circuit 106.

The receiver circuit 101 sequentially receives data from the drivercircuit DV, so that data held in the holding circuit DH in thedemultiplexer 104 varies sequentially. When the receiver circuit 101receives data, for example, the data D0 held by the data holding circuitd0 is held as D1 by the data holding circuit d1, the data D−1 held bythe data holding circuit dp is held as the reference data D0 by the dataholding circuit do, and the code of the next symbol is held by the dataholding circuit dp. Thereby, the receiver circuit 101 outputs thereference data D0, which is equalized by using the received data as thereference data D0, as DD0.

In this way, the calculation of the tap coefficient in the tapcoefficient calculation circuit 105 is controlled based on the referencedata D0 and the data D−1 one symbol after the reference data D0, so thatit is possible to improve the convergence accuracy of the tapcoefficient and shorten the convergence time. This will be describedwith reference to FIGS. 2A to 2C and 3.

FIGS. 2A to 2C are waveform charts schematically illustrating anoperation of the decision feedback equalizer (DFE circuit) 103. FIG. 2Aillustrates a waveform (transfer terminal waveform) supplied to thetransmission line DL by the driver circuit DV (FIG. 1). FIG. 2Billustrates a waveform (DFE circuit input waveform) when the waveformillustrated in FIG. 2A reaches the DFE circuit 103 through thetransmission line DL (FIG. 1) and the input buffer 102. FIG. 2Cillustrates an output waveform of the DFE circuit 103 (DFE circuitequalization waveform). In FIGS. 2A to 2C, the vertical axis representsa voltage and the horizontal axis represents time. Here, different fromFIG. 10 described above, FIGS. 2A to 2C show the times t1 to t0 beforethe time t0 on the right side of the time t0 and shows the time t−1after the time t0 on the left side of the time t0.

For ease of description, FIG. 2A illustrates a waveform in a case wherethe driver circuit DV supplies, for example, the reference data D0 oflogical value 1 to the transmission line DL at around the time t0. FIGS.2B and 2C illustrate a waveform generated by an isolated bit response inthe transmission line DL when the reference data D0 shown in FIG. 2A issupplied by the transmission line DL.

The waveform of the reference data D0 supplied to the transmission lineDL is deformed so that the bottom of the waveform becomes wider due to aloss caused by the transmission line DL. At the times t1 to t4,waveforms of the other data supplied from the driver circuit DV to thetransmission line DL are also deformed. Due to the effects of thedeformed waveforms of the other data, the waveform of the reference dataD0 supplied to the transmission line DL at around the time t0 isdeformed as shown at the times t1 to t4 in FIG. 2B. Further, while thedata D−1 is supplied from the driver circuit DV at the time t−1, thewaveform of the data D−1 is also deformed by a loss of the transmissionline DL. Therefore, due to the effects of the deformed waveform of thedata D−1, the waveform of the reference data D0 is deformed as shown atthe time t−1 in FIG. 2B.

In the decision feedback equalizer 103, the equalization is performed onthe reference data D0 based on data of a time before the reference dataD0. Specifically, the data D1 to D4 obtained by the sampling of the datasampler 121 at each time t1 to t4 before (prior to) the time t0 aresupplied to the tap coefficient multiplying circuit 124 as the outputdata B1 to B4 from the bit shift circuit 123. In the tap coefficientmultiplying circuit 124, the output data B1 to B4 are multiplied by thetap coefficients Tap1 to Tap4, and the multiplication result obtained bythe tap coefficient multiplying circuit 124 is subtracted from the inputsignal of the DFE circuit 103 in the tap adding circuit 125.

In this way, the subtraction is performed in the tap adding circuit 125,so that as illustrated in FIG. 2C, the waveform of the reference data D0before the time t0 (at the times t1 to t4) is equalized by the DFEcircuit. Therefore, it is possible to reduce the intersymbolinterference generated by the symbols before the reference data D0. Thatis to say, the decision feedback equalizer 103 is a circuit thatmultiplies data sampled in the past by the tap coefficient and feedsback the product of the multiplication to the waveform of the data D0.

The data sampler 121 samples the waveform of the reference data D0 atthe time t0, so that the code of the data received by the receivercircuit 101 is fixed.

The decision feedback equalizer 103 uses data sampled in the past, sothat it is difficult to equalize the effects of the intersymbolinterference caused by the symbols after the reference data D0.Therefore, interference remains in the waveform of the reference dataD0.

In particular, when the tap coefficients Tap1 to Tapn are determined byusing the least mean square (LMS) algorithm, if the intersymbolinterference due to data after one symbol is large, convergence propertyis degraded. In a transmission path that causes large loss, theintersymbol interference due to data after one symbol is also large, sothat the transmission path is easily affected by the convergenceproperty of the tap coefficients. Therefore, it is possible to improvethe convergence property of the tap coefficients Tap1 to Tapn andshorten the convergence time by inserting the filter circuit 106.

The equalizer will be described in further detail with reference to FIG.3. FIG. 3 is a waveform chart illustrating a waveform of the input dataIW that is an output of the tap adding circuit 125 illustrated inFIG. 1. In FIG. 3, the vertical axis represents a voltage and thehorizontal axis represents time. FIG. 3 illustrates temporallyoverlapped waveforms of the input data IW when an input signal from theinput buffer 102 is supplied to the decision feedback equalizer 103 andequalization is repetitively performed. In other words, FIG. 3illustrates a so-called eye pattern of the input data IW. The tapcoefficients Tap1 to Tapn change during the equalization, so that thevalue subtracted by the tap adding circuit 125 changes. Therefore, thewaveform of the input data IW changes and passes through the inside ofan area indicated by dots. When the values of the tap coefficients Tap1to Tapn come close to an ideal value obtained by, for example,calculation, the area indicated by dots is reduced and the areaindicated as eye in FIG. 3 is increased. When the so-called eye isexpanded and the tap coefficients Tap1 to Tapn reach the ideal value,the area indicated by dots is represented by a line.

In FIG. 3, t0 indicates a time (the reference time) when the datasampler 121 and the error sampler 122 sample the reference data D0 andt−1 indicates a time when the data sampler 121 and the error sampler 122sample the data D−1 one symbol after the reference data D0. When thetime t0 is defined as a reference, the time t−1 is temporally after thetime t0. Although not illustrated in FIG. 3, there is the time t1 beforethe time t0 on the left side of the time t0. At the time t1, the data D1one symbol before the reference data D0 is sampled.

In FIG. 3, each of dashed lines IW, IW1A to IW4A, and IW1B to IW4Brepresents an example of waveform of the input data IW. The input dataIW changes as shown by the dashed line IW at the time t1 (not shown inFIG. 3) and, at around the time t0, the input data IW changes as shownby any one of the dashed lines IW1A to IW4A and IW1B to IW4B accordingto a code (a logical value) of each of the reference data D0 and thedata D−1 one symbol after the reference data D0.

For example, when the code of the data D0 is 1, the input data IWchanges as shown by the dashed line IW1 (generic name of the dashedlines IW1A and IW1B) or IW2 (generic name of the dashed lines IW2A andIW2B), and when the code of the data D0 is 0, the input data IW changesas shown by the dashed line IW3 (generic name of the dashed lines IW3Aand IW3B) or IW4 (generic name of the dashed lines IW4A and IW4B).Further, the input data IW changes as shown by the dashed lines where acode A or a code B is attached to the codes IW1 to IW4 according to thecode of the data D−1 one symbol after the reference data D0. In otherwords, when the code of the data D−1 is 1, the input data IW changes asshown by the dashed lines to which the code A is given (IW1A to IW4A),and when the code of the data D−1 is 0, the input data IW changes asshown by the dashed lines to which the code B is given (IW1B to IW4B).

When the code (logical value) of the data D0 is 1 and the code of thedata D−1 is 1, the input data IW changes at around the time t0 as shownby the dashed line to which the code IW1A or IW2A is given, and when thecode (logical value) of the data D0 is 1 and the code of the data D−1 is0, the input data IW changes at around the time t0 as shown by thedashed line to which the code IW1B or IW2B is given. Similarly, when thecode (logical value) of the data D0 is 0 and the code of the data D−1 is1, the input data IW changes at around the time t0 as shown by thedashed line to which the code IW3A or IW4A is given, and when the code(logical value) of the data D0 is 0 and the code of the data D−1 is 0,the input data IW changes at around the time t0 as shown by the dashedline to which the code IW3B or IW4B is given.

In this way, the waveform of the input data IW changes due to the effectof the data D−1 after one symbol at the time t0 at which the referencedata D0 is sampled. For example, when the code of the reference data D0is 1, the waveform of the input data IW changes as shown by the dashedline IW1A (IW2A) or the dashed line IW1B (IW2B) depending on the code ofthe data D−1 after one symbol. Therefore, the voltage of the input dataIW′ becomes a different value depending on the code of the data D−1after one symbol at the time t0 at which the reference data D0 issampled. When the code of the reference data D0 is 0, in the samemanner, the voltage of the input data IW becomes a different valuedepending on the code of the data D−1 at the time t0 at which thereference data D0 is sampled. In other words, as illustrated in FIGS. 2Ato 2C, the intersymbol interference due to the data D−1 after one symboloccurs.

To cause the tap coefficients Tap1 to Tapn to come close to an idealvalue and to enlarge the eye, for example, it is required to identifywhether the input data IW changes as shown by the dashed line IW1A orchanges as shown by the dashed line IW1B at the time t0. It is possibleto perform the above identification by, for example, setting the dataoffset Vof supplied to the error sampler 122 to a value between thevoltage indicated by the dashed line IW1A and the voltage indicated bythe dashed line IW1B. However, in this case, it is required to set anappropriate value to the data offset Vof to be supplied to the errorsampler 122, and also a time t0 perform the identification is required.Therefore, a time t0 cause the tap coefficients Tap1 to Tapn to comeclose to an ideal value, that is to say, the convergence time of the tapcoefficients Tap1 to Tapn, increases.

Further, for example, either one of the tap coefficient corresponding tothe dashed line IW1A and the tap coefficient corresponding to the dashedline IW1B is obtained, so that a tap coefficient far different from anideal value may be obtained. Therefore, it is considered that theaccuracy of the obtained tap coefficient degrades.

FIG. 3 illustrates a combination of the codes of the reference data D0and the data D−1 as (D0, D−1). For example, the dashed line to which thecode IW1A is given indicates a case of a combination (1, 1).

In the first embodiment, when the code of the reference data D0 and thecode of the data D−1 after one symbol are coincident with each other,the update of the tap coefficients Tap1 to Tapn is allowed, and whenthese codes are not coincident with each other, the update of the tapcoefficients Tap1 to Tapn is prohibited. Thereby, the input data IWillustrated in FIG. 3 changes as illustrated by the dashed line IW1A,IW2A, IW3B, or IW4B and does not change as illustrated by the dashedlines IW1B, IW2B, IW3A, and IW4A. In other words, the input data IW isallowed to change along a waveform (the dashed line IW1A, IW2A, IW3B, orIW4B) curve of when these codes are coincident with each other (thecombination is 1, 1 or 0, 0) and is prohibited to change along awaveform (the dashed line IW1B, IW2B, IW3A, or IW4A) curve of when thesecodes are not coincident with each other (the combination is 1, 0 or 0,1). In FIG. 3, a circle mark indicates that the input data IW thatchanges as illustrated by the dashed line IW1A, IW2A, IW3B, or IW4B issampled at the time t0 to obtain the reference data D0. In this case,the value of the data offset Vof supplied to the error sampler 122 maybe a voltage value of the dashed line IW1A, IW2A, IW3B, or IW4B. Forexample, when the input data IW changes as illustrated by the dashedline IW1A or IW2A, the voltage of the dashed line IW1A at the time t0may be used as the value of the data offset Vof.

Thereby, it is possible to reduce the time to perform theidentification, so that it is possible to shorten the convergence time.When the input data IW changes as illustrated by the dashed line IW1A,IW2A, IW3B, or IW4B due to, for example, the intersymbol interferencecaused by the loss of the transmission line DL and/or the communicationspeed, it is possible to accurately obtain a tap coefficient close to anideal tap coefficient.

Next, configurations of the tap coefficient calculation circuit 105 andthe filter circuit 106 illustrated in FIG. 1 will be described. FIG. 4is a block diagram illustrating the configurations of the tapcoefficient calculation circuit 105 and the filter circuit 106 accordingto the first embodiment.

The tap coefficient calculation circuit 105 includes two-input exclusiveOR circuits 401-1 to 401-n corresponding to the data D1 to Dn andup/down counters 400-1 to 400-n corresponding to the data D1 to Dn. Eachof the data D1 to Dn from the demultiplexer 104 (FIG. 1) is supplied toone input of the exclusive OR circuits 401-1 to 401-n and the error dataE0 from the demultiplexer 104 is commonly supplied to the other input ofthe exclusive OR circuits 401-1 to 401-n. Outputs of the exclusive ORcircuits 401-1 to 401-n, to which data corresponding the up/downcounters 400-1 to 400-n are supplied, are supplied to the up/downcounters 400-1 to 400-n as up/down signals Updn-Tap1 to Updn-Tapn.Further, an update control signal Update that controls update issupplied to the up/down counters 400-1 to 400-n from the filter circuit106.

Each of the up/down counters 400-1 to 400-n is enabled to perform anup/down operation when the update control signal Update from the filtercircuit 106 is low level (logical value 0) and is prohibited to performan up/down operation when the update control signal Update from thefilter circuit 106 is high level (logical value 1). Count values of theup/down counters 400-1 to 400-n are supplied to the corresponding tapcoefficient multipliers 124-1 to 124-n (FIG. 1) as the tap coefficientsTap1 to Tapn.

Each of the exclusive OR circuits 401-1 to 401-n performs an exclusiveOR operation between the supplied error data E0 and the data D1 to Dnand outputs the operation result as the up/down signals Updn-Tap1 toUpdn-Tapn. When the update control signal Update is a logical value 0,each of the up/down counters 400-1 to 400-n increments or decrements thecount value according to the up/down signals Updn-Tap1 to Updn-Tapn.

On the other hand, when the update control signal Update is a logicalvalue 1, each of the up/down counters 400-1 to 400-n does not incrementor decrement the count value regardless of the up/down signals Updn-Tap1to Updn-Tapn. Therefore, the count values that are maintained withoutbeing incremented or decremented are supplied to the tap coefficientmultipliers 124-1 to 124-n as the tap coefficients Tap1 to Tapn.

The filter circuit 106 includes a two-input exclusive OR circuit 402that receives the reference data D0 and the data D−1 after one symbolfrom the demultiplexer 104. The exclusive OR circuit 402 performs anexclusive OR operation between the reference data D0 and the data D−1.The result of the exclusive OR operation is output to the filter circuit106 as the update control signal Update. Therefore, when the logicalvalue of the reference data D0 and the logical value of the data D−1after one symbol are coincident with each other, the logical value ofthe update control signal Update becomes 0, and when these logicalvalues are not coincident with each other, the logical value of theupdate control signal Update becomes 1.

Thereby, when codes (logical values) are coincident with each otherbetween the reference data D0 and the data D−1 one symbol after thereference data D0, the tap coefficient calculation circuit 105 updatesthe tap coefficients Tap1 to Tapn. In this case, each of the tapcoefficients Tap1 to Tapn is incremented or decremented according to aresult of an exclusive OR operation between the codes (logical values)of the data D1 to Dn of symbols before the reference data D0 and thecode (logical value) of the error data E0, so that the update isperformed. On the other hand, when the codes (logical values) are notcoincident with each other between the reference data D0 and the dataD−1 one symbol after the reference data D0, each of the tap coefficientsTap1 to Tapn is not updated but maintained.

Modified Example

FIG. 5 is a block diagram illustrating a configuration of a filtercircuit according to a modified example of the first embodiment. FIG. 5illustrates a configuration of a tap coefficient calculation circuit 105in addition to the filter circuit according to the modified example.However, the configuration of the tap coefficient calculation circuit105 is the same as that of the tap coefficient calculation circuit 105illustrated in FIG. 4, so that the description thereof will be omitted.

The filter circuit 106 according to the modified example includes anexclusive OR circuit 402 that receives the reference data D0 and thedata D−1 one symbol after the reference data D0 and a selector 500. Theselector 500 includes two input terminals I1 and I2, a selectionterminal S, and an output terminal O. The output of the exclusive ORcircuit 402 is supplied to the input terminal I1 of the selector 500,and a logical value 0 (low level) is supplied to the input terminal I2.The update control signal Update is output from the output terminal O ofthe selector 500.

Although not limited in particular, a filter enable signal FC issupplied to the selection terminal S from a control circuit (notillustrated in FIG. 5) provided outside the receiver circuit 101 (FIG.1). When the filter enable signal FC is, for example, high level(logical value 1), the selector 500 transmits the output of theexclusive OR circuit 402 which is supplied to the input terminal I1 tothe output terminal O. On the other hand, when the filter enable signalFC is low level (logical value 0), the selector 500 transmits thelogical value 0 (low level) which is supplied to the input terminal I2to the output terminal O.

When the filter enable signal FC is set to a high level by a controlcircuit not illustrated in FIG. 5, the output of the exclusive ORcircuit 402 is supplied to the tap coefficient calculation circuit 105as the update control signal Update through the selector 500. In thiscase, in the same manner as the description of FIG. 4, when the code ofthe reference data D0 and the code of the data D−1 are coincident witheach other, the update of the tap coefficients is allowed, and whenthese codes are not coincident with each other, the update of the tapcoefficients is prohibited.

On the other hand, when the filter enable signal FC is set to a lowlevel by the control circuit not illustrated in FIG. 5, the selector 500outputs a logical value 0 as the update control signal Update.Therefore, regardless of the codes (logical values) of the referencedata D0 and the data D−1, the up/down counters 400-1 to 400-n updates(increments or decrements) the count values according to the up/downsignals Updn-Tap1 to Updn-Tapn. In other words, the function of thefilter circuit 106 is disabled.

It is considered that the effect of the intersymbol interferencegenerated by the data D−1 one symbol after the reference data D0 changesdue to the loss of the transmission line DL and/or the communicationspeed. Therefore, it is considered that the effectiveness of prohibitingthe update of the tap coefficients Tap1 to Tapn changes. In thismodified example, when the effectiveness is low, the filter enablesignal FC is set to a low level by a control circuit. Thereby, the tapcoefficients are updated at all times based on the data D1 to Dn and theerror data E0.

As a result, it is possible to provide an equalizer according to atransmission line and/or a communication speed.

Second Embodiment

FIG. 6 is a block diagram illustrating a configuration of a filtercircuit 106 according to a second embodiment. FIG. 6 also illustrates aconfiguration of a tap coefficient calculation circuit 105 in additionto the filter circuit 106. The configuration of the tap coefficientcalculation circuit 105 illustrated in FIG. 6 is the same as that of thetap coefficient calculation circuit 105 illustrated in FIG. 4, so thatthe description thereof will be omitted.

In the second embodiment, the configuration of the filter circuit 106 isdifferent from that in FIG. 4. In the second embodiment, the filtercircuit 106 includes an exclusive NOR circuit 600 that receives thereference data D0 and the data D−1 one symbol after the reference dataD0. When the code (logical value) of the reference data D0 and the code(logical value) of the data D−1 after one symbol are not coincident witheach other, the exclusive NOR circuit 600 outputs the update controlsignal Update of a low level (logical value 0), and when these codes arecoincident with each other, the exclusive NOR circuit 600 outputs theupdate control signal Update of a high level (logical value 1).

Therefore, when the code of the reference data D0 and the code of thedata D−1 after one symbol are not coincident with each other, each ofthe up/down counters 400-1 to 400-n is incremented or decrementedaccording to the up/down signals Updn-Tap1 to Updn-Tapn. The incrementedor decremented count values are output from the tap coefficientcalculation circuit 105 as the tap coefficients Tap1 to Tapn.

FIG. 7 is a waveform chart illustrating a waveform of input data outputfrom a tap adding circuit 125 according to the second embodiment. FIG. 7illustrates a waveform illustrating a waveform of the input data IW inthe same manner as the waveform chart illustrated in FIG. 3. In otherwords, FIG. 7 illustrates an eye pattern of the input data IW. Differentfrom the first embodiment, in the second embodiment, when the code ofthe reference data D0 and the code of the data D−1 after one symbol arenot coincident with each other, the update of the tap coefficients Tap1to Tapn is performed. Therefore, the input data IW changes asillustrated by the dashed line IW1B, IW2B, IW3A, or IW4A. In this case,the data sampler 121 and the error sampler 122 sample the input data IWat the time t0 which is the sampling timing of the reference data D0. Atthis time, the waveform of the input data IW to be sampled changes asillustrated by any one of the dashed lines IW1B, IW2B, IW3A, and IW4A,so that the sampling is performed at a part indicated by a circle mark.

In the same manner as in the first embodiment, it is possible to shortenthe time required to perform the identification, so that it is possibleto shorten the convergence time. Further, when the input data IW changesas illustrated by the dashed line IW1B, IW2B, IW3A, or IW4A due to theintersymbol interference caused by the loss of the transmission line DLand/or the communication speed, it is possible to accurately obtain atap coefficient close to an ideal tap coefficient.

The value of the data offset Vof supplied to the error sampler 122 atthe time t0 may be a voltage of the dashed line IW1A, IW2A, IW3B, orIW4B at the time t0. When the voltage value of the data offset Vof is apotential with respect to a reference voltage Vref illustrated in FIG.7, the voltage value of the data offset Vof may be smaller than that inthe first embodiment. Therefore, a voltage range used for comparisonwhen the error sampler 122 performs the sampling can be smaller thanthat in the first embodiment.

Third Embodiment

FIG. 8 is a block diagram illustrating a configuration of a receivercircuit according to a third embodiment. The configuration of thereceiver circuit 101 illustrated in FIG. 8 is similar to theconfiguration of the receiver illustrated in FIG. 1. Here, differencesfrom the receiver circuit illustrated in FIG. 1 will be mainlydescribed. In FIG. 8, the holding circuit DH, the driver circuit DV, andthe transmission line DL which are illustrated in FIG. 1 are omitted.

In the receiver circuit 101 illustrated in FIG. 8, the tap coefficientcalculation circuit 105 forms an offset coefficient Offset to besupplied to the error sampler 122. The error sampler 122 uses the offsetcoefficient Offset formed by the tap coefficient calculation circuit 105as the data offset Vof and samples the input data IW based on the dataoffset.

In the third embodiment, the tap coefficient calculation circuit 105uses the reference data D0 and the error data E0 to form the offsetcoefficient Offset. Therefore, the reference data D0 is also supplied tothe tap coefficient calculation circuit 105 as compared with the tapcoefficient calculation circuit illustrated in FIG. 1.

FIG. 9 is a block diagram illustrating a configuration of the tapcoefficient calculation circuit 105 according to the third embodiment.FIG. 9 illustrates a configuration of a filter circuit 106 in additionto the tap coefficient calculation circuit 105. However, theconfiguration of the filter circuit 106 is the same as the configurationof the filter circuit 106 described in FIG. 4, so that the descriptionthereof will be omitted.

In the configuration of the tap coefficient calculation circuit 105illustrated in FIG. 9, a circuit that forms the offset coefficientOffset is added with respect to the tap coefficient calculation circuit105 illustrated in FIG. 4. First, the same part between the tapcoefficient calculation circuit illustrated in FIG. 9 and tapcoefficient calculation circuit illustrated in FIG. 4 will be described.The configuration of the up/down counters 400-1 to 400-n and theexclusive OR circuits 401-1 to 401-n in FIG. 9 is the same as theconfiguration of the up/down counters 400-1 to 400-n and the exclusiveOR circuits 401-1 to 401-n in FIG. 4. In other words, a configuration ofa part where the tap coefficients Tap1 to Tapn are formed is the samebetween FIGS. 9 and 4. Therefore, the description of the part where thetap coefficients Tap1 to Tapn are formed will be omitted.

As compared with FIG. 4, an up/down counter 900 and an exclusive NORcircuit 901 are added to the tap coefficient calculation circuit 105illustrated in FIG. 9. The up/down counter 900 and the exclusive NORcircuit 901 form a circuit that forms the offset coefficient Offset. Theexclusive NOR circuit 901 has two input ports, the reference data D0 issupplied to one input port of the two input ports, and the error data E0is supplied to the other input port. The output of the exclusive NORcircuit 901 is supplied to the up/down counter 900 as an offset up/downsignal Updn-Offset. The update control signal Update is further suppliedto the up/down counter 900 and a count value of the up/down counter 900is output from the tap coefficient calculation circuit 105 as the offsetcoefficient Offset.

In the same manner as the up/down counters 400-1 to 400-n, the up/downcounter 900 is allowed to perform an up/down operation when the updatecontrol signal Update is low level (logical value 0), and the up/downcounter 900 is prohibited to perform an up/down operation when theupdate control signal Update is high level (logical value 1). When theup/down counter 900 is allowed to perform the up/down operation, thatis, when the update control signal Update is the low level, the up/downcounter 900 performs an up operation or a down operation according to asupplied offset up/down signal Updn-Offset. A count value that isincremented by the up operation or a count value that is decremented bythe down operation is output from the tap coefficient calculationcircuit 105 as the offset coefficient Offset.

The exclusive NOR circuit 901 outputs the offset up/down signalUpdn-Offset according to a combination of the code (logical value) ofthe reference data D0 and the code of the error data E0 (logical value).When the update is allowed by the update control signal Update, that is,when the update control signal Update is low level, the up/down counter900 performs count up or count down according to the up/down signalUpdn-Offset. A count value obtained by the count up or the count down isused as the data offset Vof of the error sampler 122. Therefore, it ispossible to automatically adjust the data offset supplied to the errorsampler 122 based on the reference data D0 and the error data E0.

The update of the up/down counter 900 is allowed by the update controlsignal Update from the filter circuit 106 only when the code of thereference data D0 and the code of the data D−1 after one symbol arecoincident with each other. Therefore, a corresponding data offset isformed when the code of the reference data D0 and the code of the dataD−1 after one symbol are coincident with each other, so that it ispossible to improve the convergence property and the stability of thedata offset supplied to the error sampler 122 as compared with a casewhere the data offset is formed regardless of the reference data D0 andthe data D−1.

The update of the tap coefficients Tap1 to Tapn and the update of theoffset coefficient Offset are controlled by the update control signalUpdate, so that it is possible to adjust the offset coefficient Offset,which is a data offset supplied to the error sampler 122, according to achange of the input data IW. In FIG. 3, when the input data 1W changesas illustrated by the dashed line IW1A or IW2A, it is possible that theoffset coefficient Offset indicates a voltage of the dashed line IW1A(IW2A) at the time t0. In the same manner, in FIG. 3, when the inputdata IW changes as illustrated by the dashed line IW3B or IW4B, it ispossible that the offset coefficient Offset indicates a voltage of thedashed line IW3B (IW4B) at the time t0.

In FIGS. 8 and 9, in the same manner as in the first embodiment, anexample is described in which the offset coefficient Offset is updatedwhen the code of the reference data D0 and the code of the data D−1after one symbol are coincident with each other. However, as describedin the second embodiment, the offset coefficient Offset may be updatedwhen the code of the reference data D0 and the code of the data D−1after one symbol are not coincident with each other.

Further, in the second and the third embodiments, as described in themodified example of the first embodiment, the enable/disable of thefunction of the filter circuit 106 may be controlled by the filterenable signal FC.

The tap coefficient calculation circuit 105 and the filter circuit 106are not limited to the configurations described in the first to thethird embodiments, but can have various configurations.

Further, in the first to the third embodiments, the presence or absenceof the update is controlled based on the code of the reference data D0and the code of the data after one symbol. However, it is not limited tothis. For example, the presence or absence of the update may becontrolled based on the code of data a plurality of symbols after thereference data D0 instead of the code of data one symbol after thereference data D0 and the code of the reference data D0. Further, thepresence or absence of the update may be controlled based on the codesof data of a plurality of symbols after the reference data D0 and thecode of the reference data D0.

While the invention made by the inventors has been specificallydescribed based on the embodiments, it is needless to say that thepresent invention is not limited to the embodiments and may be variouslymodified without departing from the scope of the invention.

What is claimed is:
 1. An equalizer comprising: a data sampler thatsamples input data and outputs a time-series data string according tothe input data; an arithmetic circuit that multiplies a data stringoutput before reference data in the data string output from the datasampler by a tap coefficient and forms the input data by an arithmeticoperation of a multiplication result and an input signal; a tapcoefficient calculation circuit that updates the tap coefficient basedon a data string output before the reference data; and a determinationcircuit that receives the reference data and data output after thereference data in the data string and controls presence or absence ofupdate of the tap coefficient performed by the tap coefficientcalculation circuit.
 2. The equalizer according to claim 1, furthercomprising: an error sampler that samples the input data based on apredetermined offset, wherein the tap coefficient calculation circuitupdates the tap coefficient based on a data string output before thereference data in the data string output from the data sampler and errordata output from the error sampler.
 3. The equalizer according to claim2, further comprising: a holding circuit that holds the data stringoutput from the data sampler and the error data output from the errorsampler, wherein a data string output before the reference data and theerror data which are held by the holding circuit are supplied to the tapcoefficient calculation circuit, and the reference data and data outputafter the reference data which are held by the holding circuit aresupplied to the determination circuit.
 4. The equalizer according toclaim 3, wherein the error sampler forms a time-series error data stringaccording to the input data, and in the formed error data string, errordata corresponding to the reference data is held by the holding circuit.5. An equalizer including an input buffer that receives an input signal,a decision feedback equalizer including a data sampler and an errorsampler, and a tap coefficient calculation circuit that receives a dataoutput from the data sampler and an error output from the error samplerand adaptively calculates a tap coefficient in the decision feedbackequalizer, the equalizer comprising: a filter circuit that receives dataof a predetermined one symbol to be reference data in the data outputfrom the data sampler and data one symbol after the predetermined onesymbol, wherein presence or absence of update of the tap coefficient inthe tap coefficient calculation circuit is determined according to aresult of the filter circuit.
 6. The equalizer according to claim 5,wherein the filter circuit performs an exclusive OR operation betweenthe reference data and the data after one symbol, and when an operationresult of the exclusive OR operation indicates coincidence, the filtercircuit updates the tap coefficient in the tap coefficient calculationcircuit.
 7. The equalizer according to claim 5, wherein the filtercircuit performs an exclusive NOR operation between the reference dataand the data after one symbol, and when an operation result of theexclusive NOR, operation indicates non-coincidence, the filter circuitupdates the tap coefficient in the tap coefficient calculation circuit.8. The equalizer according to claim 5, wherein an enable signal thatdisables a function of the filter circuit is supplied to the filtercircuit.
 9. The equalizer according to claim 5, wherein the filtercircuit receives the reference data and data of a plurality of symbolsafter the predetermined symbol.
 10. The equalizer according to claim 5,wherein the error sampler performs sampling based on an offset accordingto an offset coefficient and presence or absence of update of the offsetcoefficient is controlled by the filter circuit.
 11. The equalizeraccording to claim 10, wherein when the update of the offset coefficientis allowed by the filter circuit, the update of the offset coefficientis performed based on the reference data and the error output.